Merge branch 'master' into develop
This commit is contained in:
commit
cbf8072072
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@ -108,7 +108,7 @@ static void ntp_recv(void *arg, struct udp_pcb *pcb, struct pbuf *p, const ip_ad
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// Perform initialisation
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static NTP_T* ntp_init(void) {
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NTP_T *state = calloc(1, sizeof(NTP_T));
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NTP_T *state = (NTP_T*)calloc(1, sizeof(NTP_T));
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if (!state) {
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printf("failed to allocate state\n");
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return NULL;
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@ -183,4 +183,4 @@ int main() {
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run_ntp_test();
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cyw43_arch_deinit();
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return 0;
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}
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}
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@ -1,5 +1,5 @@
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/**
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* Copyright (c) 2021 pmarques-dev @ github
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* Copyright (c) 2023 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -44,8 +44,10 @@ int main() {
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PIO pio = pio0;
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const uint sm = 0;
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uint offset = pio_add_program(pio, &quadrature_encoder_program);
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quadrature_encoder_program_init(pio, sm, offset, PIN_AB, 0);
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// we don't really need to keep the offset, as this program must be loaded
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// at offset 0
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pio_add_program(pio, &quadrature_encoder_program);
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quadrature_encoder_program_init(pio, sm, PIN_AB, 0);
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while (1) {
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// note: thanks to two's complement arithmetic delta will always
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@ -1,13 +1,12 @@
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;
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; Copyright (c) 2021 pmarques-dev @ github
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; Copyright (c) 2023 Raspberry Pi (Trading) Ltd.
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;
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; SPDX-License-Identifier: BSD-3-Clause
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;
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.program quadrature_encoder
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; this code must be loaded into address 0, but at 29 instructions, it probably
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; wouldn't be able to share space with other programs anyway
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; the code must be loaded at address 0, because it uses computed jumps
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.origin 0
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@ -20,82 +19,70 @@
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; keeps the current encoder count and is incremented / decremented according to
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; the steps sampled
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; writing any non zero value to the TX FIFO makes the state machine push the
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; current count to RX FIFO between 6 to 18 clocks afterwards. The worst case
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; sampling loop takes 14 cycles, so this program is able to read step rates up
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; to sysclk / 14 (e.g., sysclk 125MHz, max step rate = 8.9 Msteps/sec)
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; the program keeps trying to write the current count to the RX FIFO without
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; blocking. To read the current count, the user code must drain the FIFO first
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; and wait for a fresh sample (takes ~4 SM cycles on average). The worst case
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; sampling loop takes 10 cycles, so this program is able to read step rates up
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; to sysclk / 10 (e.g., sysclk 125MHz, max step rate = 12.5 Msteps/sec)
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; 00 state
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JMP update ; read 00
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JMP decrement ; read 01
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JMP increment ; read 10
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JMP update ; read 11
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JMP update ; read 00
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JMP decrement ; read 01
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JMP increment ; read 10
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JMP update ; read 11
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; 01 state
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JMP increment ; read 00
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JMP update ; read 01
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JMP update ; read 10
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JMP decrement ; read 11
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JMP increment ; read 00
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JMP update ; read 01
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JMP update ; read 10
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JMP decrement ; read 11
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; 10 state
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JMP decrement ; read 00
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JMP update ; read 01
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JMP update ; read 10
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JMP increment ; read 11
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JMP decrement ; read 00
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JMP update ; read 01
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JMP update ; read 10
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JMP increment ; read 11
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; to reduce code size, the last 2 states are implemented in place and become the
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; target for the other jumps
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; 11 state
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JMP update ; read 00
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JMP increment ; read 01
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JMP update ; read 00
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JMP increment ; read 01
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decrement:
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; note: the target of this instruction must be the next address, so that
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; the effect of the instruction does not depend on the value of Y. The
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; same is true for the "JMP X--" below. Basically "JMP Y--, <next addr>"
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; is just a pure "decrement Y" instruction, with no other side effects
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JMP Y--, update ; read 10
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; note: the target of this instruction must be the next address, so that
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; the effect of the instruction does not depend on the value of Y. The
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; same is true for the "JMP X--" below. Basically "JMP Y--, <next addr>"
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; is just a pure "decrement Y" instruction, with no other side effects
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JMP Y--, update ; read 10
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; this is where the main loop starts
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; this is where the main loop starts
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.wrap_target
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update:
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; we start by checking the TX FIFO to see if the main code is asking for
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; the current count after the PULL noblock, OSR will have either 0 if
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; there was nothing or the value that was there
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SET X, 0
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PULL noblock
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; since there are not many free registers, and PULL is done into OSR, we
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; have to do some juggling to avoid losing the state information and
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; still place the values where we need them
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MOV X, OSR
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MOV OSR, ISR
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; the main code did not ask for the count, so just go to "sample_pins"
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JMP !X, sample_pins
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; if it did ask for the count, then we push it
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MOV ISR, Y ; we trash ISR, but we already have a copy in OSR
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PUSH
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MOV ISR, Y ; read 11
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PUSH noblock
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sample_pins:
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; we shift into ISR the last state of the 2 input pins (now in OSR) and
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; the new state of the 2 pins, thus producing the 4 bit target for the
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; computed jump into the correct action for this state
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MOV ISR, NULL
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IN OSR, 2
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IN PINS, 2
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MOV PC, ISR
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; we shift into ISR the last state of the 2 input pins (now in OSR) and
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; the new state of the 2 pins, thus producing the 4 bit target for the
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; computed jump into the correct action for this state. Both the PUSH
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; above and the OUT below zero out the other bits in ISR
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OUT ISR, 2
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IN PINS, 2
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; the PIO does not have a increment instruction, so to do that we do a
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; negate, decrement, negate sequence
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; save the state in the OSR, so that we can use ISR for other purposes
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MOV OSR, ISR
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; jump to the correct state machine action
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MOV PC, ISR
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; the PIO does not have a increment instruction, so to do that we do a
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; negate, decrement, negate sequence
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increment:
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MOV X, !Y
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JMP X--, increment_cont
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MOV Y, ~Y
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JMP Y--, increment_cont
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increment_cont:
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MOV Y, !X
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.wrap ; the .wrap here avoids one jump instruction and saves a cycle too
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MOV Y, ~Y
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.wrap ; the .wrap here avoids one jump instruction and saves a cycle too
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@ -106,60 +93,49 @@ increment_cont:
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// max_step_rate is used to lower the clock of the state machine to save power
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// if the application doesn't require a very high sampling rate. Passing zero
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// will set the clock to the maximum, which gives a max step rate of around
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// 8.9 Msteps/sec at 125MHz
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// will set the clock to the maximum
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static inline void quadrature_encoder_program_init(PIO pio, uint sm, uint offset, uint pin, int max_step_rate)
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static inline void quadrature_encoder_program_init(PIO pio, uint sm, uint pin, int max_step_rate)
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{
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pio_sm_set_consecutive_pindirs(pio, sm, pin, 2, false);
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gpio_pull_up(pin);
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gpio_pull_up(pin + 1);
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pio_sm_set_consecutive_pindirs(pio, sm, pin, 2, false);
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gpio_pull_up(pin);
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gpio_pull_up(pin + 1);
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pio_sm_config c = quadrature_encoder_program_get_default_config(offset);
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sm_config_set_in_pins(&c, pin); // for WAIT, IN
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sm_config_set_jmp_pin(&c, pin); // for JMP
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// shift to left, autopull disabled
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sm_config_set_in_shift(&c, false, false, 32);
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// don't join FIFO's
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sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_NONE);
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pio_sm_config c = quadrature_encoder_program_get_default_config(0);
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// passing "0" as the sample frequency,
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if (max_step_rate == 0) {
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sm_config_set_clkdiv(&c, 1.0);
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} else {
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// one state machine loop takes at most 14 cycles
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float div = (float)clock_get_hz(clk_sys) / (14 * max_step_rate);
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sm_config_set_clkdiv(&c, div);
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}
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sm_config_set_in_pins(&c, pin); // for WAIT, IN
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sm_config_set_jmp_pin(&c, pin); // for JMP
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// shift to left, autopull disabled
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sm_config_set_in_shift(&c, false, false, 32);
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// don't join FIFO's
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sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_NONE);
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pio_sm_init(pio, sm, offset, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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// passing "0" as the sample frequency,
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if (max_step_rate == 0) {
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sm_config_set_clkdiv(&c, 1.0);
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} else {
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// one state machine loop takes at most 10 cycles
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float div = (float)clock_get_hz(clk_sys) / (10 * max_step_rate);
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sm_config_set_clkdiv(&c, div);
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}
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// When requesting the current count we may have to wait a few cycles (average
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// ~11 sysclk cycles) for the state machine to reply. If we are reading multiple
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// encoders, we may request them all in one go and then fetch them all, thus
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// avoiding doing the wait multiple times. If we are reading just one encoder,
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// we can use the "get_count" function to request and wait
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static inline void quadrature_encoder_request_count(PIO pio, uint sm)
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{
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pio->txf[sm] = 1;
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}
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static inline int32_t quadrature_encoder_fetch_count(PIO pio, uint sm)
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{
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while (pio_sm_is_rx_fifo_empty(pio, sm))
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tight_loop_contents();
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return pio->rxf[sm];
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pio_sm_init(pio, sm, 0, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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static inline int32_t quadrature_encoder_get_count(PIO pio, uint sm)
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{
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quadrature_encoder_request_count(pio, sm);
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return quadrature_encoder_fetch_count(pio, sm);
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uint ret;
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int n;
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// if the FIFO has N entries, we fetch them to drain the FIFO,
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// plus one entry which will be guaranteed to not be stale
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n = pio_sm_get_rx_fifo_level(pio, sm) + 1;
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while (n > 0) {
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ret = pio_sm_get_blocking(pio, sm);
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n--;
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}
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return ret;
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}
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%}
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